diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 698370b..52a9f39 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -770,6 +770,7 @@
 	select ARCH_LS1021A
 	select ARCH_SUPPORT_PSCI
 	select LS1_DEEP_SLEEP
+	select SYS_FSL_DDR
 
 config TARGET_LS1021ATWR
 	bool "Support ls1021atwr"
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index d154f7b..eca1d06 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -3,8 +3,10 @@
 	select SYS_FSL_ERRATUM_A010315
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
-	select SYS_FSL_DDR_BE
-	select SYS_FSL_DDR_VER_50
+	select SYS_FSL_DDR_BE if SYS_FSL_DDR
+	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
+	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
+	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_LE
@@ -49,47 +51,6 @@
 config SYS_HAS_SERDES
 	bool
 
-config SYS_FSL_DDR
-	bool "Freescale DDR driver"
-	help
-	  Select Freescale General DDR driver, shared between most Freescale
-	  PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
-	  based Layerscape SoCs (such as ls2080a).
-
-config SYS_FSL_DDR_BE
-	bool
-	default y
-	help
-	  Access DDR registers in big-endian.
-
-config SYS_FSL_DDR_VER
-	int
-	default 50 if SYS_FSL_DDR_VER_50
-
-config SYS_FSL_DDR_VER_50
-	bool
-
-config SYS_FSL_DDRC_ARM_GEN3
-	bool
-
-config SYS_FSL_DDRC_GEN4
-	bool
-
-config SYS_FSL_DDR3
-	bool "Freescale DDR3 controller"
-	depends on !SYS_FSL_DDR4
-	select SYS_FSL_DDR
-	select SYS_FSL_DDRC_ARM_GEN3
-	help
-	  Enable Freescale DDR3 controller on ARM-based SoCs.
-
-config SYS_FSL_DDR4
-	bool "Freescale DDR4 controller"
-	select SYS_FSL_DDR
-	select SYS_FSL_DDRC_GEN4
-	help
-	  Enable Freescale DDR4 controller.
-
 config SYS_FSL_IFC_BANK_COUNT
 	int "Maximum banks of Integrated flash controller"
 	depends on ARCH_LS1021A
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index a1f781e..bee7d15 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -8,28 +8,33 @@
 config ARCH_LS1043A
 	bool
 	select FSL_LSCH2
+	select SYS_FSL_DDR
 	select SYS_FSL_DDR_BE
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A010315
 	select SYS_FSL_ERRATUM_A010539
+	select SYS_FSL_HAS_DDR3
+	select SYS_FSL_HAS_DDR4
 
 config ARCH_LS1046A
 	bool
 	select FSL_LSCH2
+	select SYS_FSL_DDR
 	select SYS_FSL_DDR_BE
-	select SYS_FSL_DDR4
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_ERRATUM_A010539
+	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_SRDS_2
 
 config ARCH_LS2080A
 	bool
 	select FSL_LSCH3
-	select SYS_FSL_DDR4
+	select SYS_FSL_DDR
 	select SYS_FSL_DDR_LE
 	select SYS_FSL_DDR_VER_50
 	select SYS_FSL_HAS_DP_DDR
 	select SYS_FSL_HAS_SEC
+	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_LE
 	select SYS_FSL_SRDS_2
@@ -71,9 +76,6 @@
 	  implemented under the common ARMv8 PSCI framework.
 endmenu
 
-config SYS_FSL_MMDC
-	bool
-
 config SYS_FSL_ERRATUM_A010315
 	bool "Workaround for PCIe erratum A010315"
 
@@ -129,49 +131,4 @@
 config SYS_HAS_SERDES
 	bool
 
-config SYS_FSL_DDR
-	bool "Freescale DDR driver"
-	help
-	  Select Freescale General DDR driver, shared between most Freescale
-	  PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
-	  based Layerscape SoCs (such as ls2080a).
-
-config SYS_FSL_DDR_BE
-	bool
-	help
-	  Access DDR registers in big-endian.
-
-config SYS_FSL_DDR_LE
-	bool
-	help
-	  Access DDR registers in little-endian.
-
-config SYS_FSL_DDR_VER
-	int
-	default 50 if SYS_FSL_DDR_VER_50
-
-config SYS_FSL_DDR_VER_50
-	bool
-
-config SYS_FSL_DDRC_ARM_GEN3
-	bool
-
-config SYS_FSL_DDRC_GEN4
-	bool
-
-config SYS_FSL_DDR3
-	bool "Freescale DDR3 controller"
-	depends on !SYS_FSL_DDR4
-	select SYS_FSL_DDR
-	select SYS_FSL_DDRC_ARM_GEN3
-	help
-	  Enable Freescale DDR3 controller on ARM-based SoCs.
-
-config SYS_FSL_DDR4
-	bool "Freescale DDR4 controller"
-	select SYS_FSL_DDR
-	select SYS_FSL_DDRC_GEN4
-	help
-	  Enable Freescale DDR4 controller.
-
 endmenu
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 29fc33d..db40669 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -175,11 +175,11 @@
 #define CONFIG_SYS_FSL_ERRATUM_A009942
 #define CONFIG_SYS_FSL_ERRATUM_A009660
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC		1
-#elif defined(CONFIG_ARCH_LS1012A)
-#undef	CONFIG_SYS_FSL_DDRC_ARM_GEN3
 
+#elif defined(CONFIG_ARCH_LS1012A)
 #define GICD_BASE		0x01401000
 #define GICC_BASE		0x01402000
+
 #elif defined(CONFIG_ARCH_LS1046A)
 #define CONFIG_SYS_FMAN_V3
 #define CONFIG_SYS_NUM_FMAN			1
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 853e265..0033c35 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -30,9 +30,13 @@
 config MPC85xx
 	bool "MPC85xx"
 	select CREATE_ARCH_SYMLINK
+	select SYS_FSL_DDR
+	select SYS_FSL_DDR_BE
 
 config MPC86xx
 	bool "MPC86xx"
+	select SYS_FSL_DDR
+	select SYS_FSL_DDR_BE
 
 config 8xx
 	bool "MPC8xx"
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 3ea62ca..6e4a931 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -38,6 +38,9 @@
 
 config TARGET_MPC8349EMDS
 	bool "Support MPC8349EMDS"
+	select SYS_FSL_DDR
+	select SYS_FSL_HAS_DDR2
+	select SYS_FSL_DDR_BE
 
 config TARGET_MPC8349ITX
 	bool "Support MPC8349ITX"
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index 7b000d7..307a45d 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -68,6 +68,8 @@
 config TARGET_MPC8536DS
 	bool "Support MPC8536DS"
 	select ARCH_MPC8536
+# Use DDR3 controller with DDR2 DIMMs on this board
+	select SYS_FSL_DDRC_GEN3
 
 config TARGET_MPC8540ADS
 	bool "Support MPC8540ADS"
@@ -104,6 +106,8 @@
 config TARGET_MPC8572DS
 	bool "Support MPC8572DS"
 	select ARCH_MPC8572
+# Use DDR3 controller with DDR2 DIMMs on this board
+	select SYS_FSL_DDRC_GEN3
 
 config TARGET_P1010RDB_PA
 	bool "Support P1010RDB_PA"
@@ -300,6 +304,8 @@
 config TARGET_XPEDITE537X
 	bool "Support xpedite537x"
 	select ARCH_MPC8572
+# Use DDR3 controller with DDR2 DIMMs on this board
+	select SYS_FSL_DDRC_GEN3
 
 config TARGET_XPEDITE550X
 	bool "Support xpedite550x"
@@ -325,6 +331,7 @@
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
@@ -333,6 +340,7 @@
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
@@ -340,6 +348,7 @@
 config ARCH_BSC9131
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
@@ -347,6 +356,7 @@
 config ARCH_BSC9132
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
@@ -355,6 +365,7 @@
 config ARCH_C29X
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_6
@@ -363,6 +374,8 @@
 config ARCH_MPC8536
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR2
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
@@ -371,10 +384,12 @@
 config ARCH_MPC8540
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR1
 
 config ARCH_MPC8541
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR1
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
@@ -382,6 +397,7 @@
 config ARCH_MPC8544
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR2
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
@@ -390,6 +406,8 @@
 config ARCH_MPC8548
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR2
+	select SYS_FSL_HAS_DDR1
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
@@ -398,6 +416,7 @@
 config ARCH_MPC8555
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR1
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
@@ -405,10 +424,12 @@
 config ARCH_MPC8560
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR1
 
 config ARCH_MPC8568
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR2
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
@@ -416,6 +437,7 @@
 config ARCH_MPC8569
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
@@ -423,14 +445,17 @@
 config ARCH_MPC8572
 	bool
 	select FSL_LAW
-	select SYS_PPC_E500_USE_DEBUG_TLB
+	select SYS_FSL_HAS_DDR2
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
+	select SYS_PPC_E500_USE_DEBUG_TLB
 
 config ARCH_P1010
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
@@ -439,6 +464,7 @@
 config ARCH_P1011
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
@@ -447,6 +473,7 @@
 config ARCH_P1020
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
@@ -455,6 +482,7 @@
 config ARCH_P1021
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
@@ -463,6 +491,7 @@
 config ARCH_P1022
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
@@ -471,6 +500,7 @@
 config ARCH_P1023
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
@@ -478,6 +508,7 @@
 config ARCH_P1024
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
@@ -486,6 +517,7 @@
 config ARCH_P1025
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
@@ -494,6 +526,7 @@
 config ARCH_P2020
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_2
@@ -503,6 +536,7 @@
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
@@ -511,6 +545,7 @@
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
@@ -519,6 +554,7 @@
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
@@ -527,6 +563,7 @@
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
@@ -535,6 +572,7 @@
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
@@ -546,6 +584,8 @@
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
+	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
@@ -554,6 +594,8 @@
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
+	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
@@ -562,6 +604,8 @@
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
+	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
@@ -570,6 +614,8 @@
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
+	select SYS_FSL_HAS_DDR4
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_5
@@ -578,6 +624,7 @@
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
@@ -586,6 +633,7 @@
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
@@ -594,6 +642,7 @@
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
@@ -602,6 +651,7 @@
 	bool
 	select E500MC
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR3
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_BE
 	select SYS_FSL_SEC_COMPAT_4
diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig
index 11afffa..ff21c48 100644
--- a/arch/powerpc/cpu/mpc86xx/Kconfig
+++ b/arch/powerpc/cpu/mpc86xx/Kconfig
@@ -29,10 +29,14 @@
 config ARCH_MPC8610
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR1
+	select SYS_FSL_HAS_DDR2
 
 config ARCH_MPC8641
 	bool
 	select FSL_LAW
+	select SYS_FSL_HAS_DDR1
+	select SYS_FSL_HAS_DDR2
 
 config FSL_LAW
 	bool
diff --git a/arch/powerpc/include/asm/config.h b/arch/powerpc/include/asm/config.h
index d4f05d1..55686a1 100644
--- a/arch/powerpc/include/asm/config.h
+++ b/arch/powerpc/include/asm/config.h
@@ -9,16 +9,13 @@
 
 #ifdef CONFIG_MPC85xx
 #include <asm/config_mpc85xx.h>
-#define CONFIG_SYS_FSL_DDR
 #endif
 
 #ifdef CONFIG_MPC86xx
 #include <asm/config_mpc86xx.h>
-#define CONFIG_SYS_FSL_DDR
 #endif
 
 #ifdef CONFIG_MPC83xx
-#define CONFIG_SYS_FSL_DDR
 #endif
 
 #ifndef HWCONFIG_BUFFER_SIZE
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 4e9fcc8..6aee5bc 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -16,7 +16,6 @@
 #define CONFIG_PPC_SPINTABLE_COMPATIBLE
 
 #include <fsl_ddrc_version.h>
-#define CONFIG_SYS_FSL_DDR_BE
 
 /* IP endianness */
 #define CONFIG_SYS_FSL_IFC_BE
@@ -28,17 +27,13 @@
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_ARCH_MPC8540)
-#define CONFIG_SYS_FSL_DDRC_GEN1
 
 #elif defined(CONFIG_ARCH_MPC8541)
-#define CONFIG_SYS_FSL_DDRC_GEN1
 
 #elif defined(CONFIG_ARCH_MPC8544)
-#define CONFIG_SYS_FSL_DDRC_GEN2
 #define CONFIG_SYS_FSL_ERRATUM_A005125
 
 #elif defined(CONFIG_ARCH_MPC8548)
-#define CONFIG_SYS_FSL_DDRC_GEN2
 #define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
 #define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
 #define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
@@ -52,13 +47,10 @@
 #define CONFIG_SYS_FSL_A004447_SVR_REV	0x00
 
 #elif defined(CONFIG_ARCH_MPC8555)
-#define CONFIG_SYS_FSL_DDRC_GEN1
 
 #elif defined(CONFIG_ARCH_MPC8560)
-#define CONFIG_SYS_FSL_DDRC_GEN1
 
 #elif defined(CONFIG_ARCH_MPC8568)
-#define CONFIG_SYS_FSL_DDRC_GEN2
 #define QE_MURAM_SIZE			0x10000UL
 #define MAX_QE_RISC			2
 #define QE_NUM_OF_SNUM			28
@@ -544,9 +536,6 @@
 #define CONFIG_SYS_FSL_QORIQ_CHASSIS2	/* Freescale Chassis generation 2 */
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3		/* QMAN version 3 */
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#endif
 #define CONFIG_SYS_FSL_NUM_CC_PLLS	2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS   { 1, 1, 1, 1 }
 #define CONFIG_SYS_FSL_SRDS_1
@@ -588,9 +577,6 @@
 #define CONFIG_SYS_FSL_CORES_PER_CLUSTER 1
 #define CONFIG_SYS_FSL_QMAN_V3	 /* QMAN version 3 */
 #define CONFIG_SYS_FMAN_V3
-#ifdef CONFIG_SYS_FSL_DDR4
-#define CONFIG_SYS_FSL_DDRC_GEN4
-#endif
 #define CONFIG_SYS_FSL_NUM_CC_PLL	2
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS  { 1, 1, 1, 1 }
 #define CONFIG_SYS_FSL_SRDS_1
@@ -697,13 +683,6 @@
 #define CONFIG_SYS_FSL_THREADS_PER_CORE 1
 #endif
 
-#if !defined(CONFIG_SYS_FSL_DDRC_GEN1) && \
-	!defined(CONFIG_SYS_FSL_DDRC_GEN2) && \
-	!defined(CONFIG_SYS_FSL_DDRC_GEN3) && \
-	!defined(CONFIG_SYS_FSL_DDRC_GEN4)
-#define CONFIG_SYS_FSL_DDRC_GEN3
-#endif
-
 #if !defined(CONFIG_ARCH_C29X)
 #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC	1
 #endif
diff --git a/arch/powerpc/include/asm/config_mpc86xx.h b/arch/powerpc/include/asm/config_mpc86xx.h
index f053b9c..5eabe6d 100644
--- a/arch/powerpc/include/asm/config_mpc86xx.h
+++ b/arch/powerpc/include/asm/config_mpc86xx.h
@@ -7,6 +7,4 @@
 #ifndef _ASM_MPC86xx_CONFIG_H_
 #define _ASM_MPC86xx_CONFIG_H_
 
-#define CONFIG_SYS_FSL_DDR_86XX
-
 #endif /* _ASM_MPC85xx_CONFIG_H_ */